Digital Bench Characterization Engineer – DDR and High-Speed IO interface

Job content

Company:Qualcomm India Private Limited

Job Area:Engineering Group, Engineering Group > Hardware Engineering

Job Overview:
Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.

General Summary

The BDC Post Silicon Engineering group has an opening for a Digital Bench characterization Engineer. This group develops Test solutions for Design verification of Highly integrated SOC’s (System on Chip) designed by Qualcomm. We work with Design, System, Program Management, Yield, Reliability and Manufacturing teams to Test, support and commercialize Qualcomm’s products.
As part of the Post Silicon Engineering group, you will be responsible for developing Test strategy & executing Bench characterization for leading edge LPDDR & PCDDR Subsystem components (DRAM, DRAM Controller, DRAM PHY, IOs, PLL/DLL, clocking architecture, Delay circuits, Power Distribution Network) and High-Speed IO interfaces (PCIe, USB2/3, Display Port, HDMI, MIPI-CSI/DSI, UFS & PLL). You will drive first Silicon debug, qualify semiconductor fabrication process, evaluate parametric performance of DDR & High-Speed IO IP’s and perform failure analysis to root-cause a design problem. You with be working with IC design engineering, system engineering and Hardware applications engineering teams across the globe in a time critical environment.
Education Requirements
MTech, BTech or Equivalent in Electronics or Electrical Engineering with 1-3 years of related work experience

Skills/Experience

 Solid understanding of Electronics engineering fundamentals, DDR & High-Speed IO circuit analysis techniques and Semiconductor manufacturing process,
 Good understanding of Test and characterization methodology of DDR and High-Speed IO interfaces
 In-depth understanding of Mobile & PC DDR 2/3/4 protocol, timing diagrams, HSIO IPs PHY level understanding and Electrical parametric compliance specifications (eye diagram, differential signaling, jitter analysis, Receiver-Jitter-Tolerance, signal integrity, transmission line considerations, de-embedding).
 Hands-on experience using Bench instruments such as oscilloscopes, J-BERT, network / spectrum analyzers, signal generators and Logic analyzers is a must.
 Solid software skills for writing and debugging Test code using C, C# or Python. LabView knowledge is a plus.
 Using CAD software such as Mentor Graphics DA or Cadence Allegro is a plus.
 Ability to work effectively in a fast-paced environment with strong verbal and written communication skills.
Keywords

DDR, High-Speed IO, Electrical Spec compliance, Eye Diagram, Jitter, C, C#, Python, LabVIEW
The BDC Post Silicon Engineering group has an opening for a Digital Bench characterization Engineer. This group develops Test solutions for Design verification of Highly integrated SOC’s (System on Chip) designed by Qualcomm. We work with Design, System, Program Management, Yield, Reliability and Manufacturing teams to Test, support and commercialize Qualcomm’s products.

As part of the Post Silicon Engineering group, you will be responsible for developing Test strategy & executing Bench characterization for leading edge LPDDR & PCDDR Subsystem components (DRAM, DRAM Controller, DRAM PHY, IOs, PLL/DLL, clocking architecture, Delay circuits, Power Distribution Network) and High-Speed IO interfaces (PCIe, USB2/3, Display Port, HDMI, MIPI-CSI/DSI, UFS & PLL). You will drive first Silicon debug, qualify semiconductor fabrication process, evaluate parametric performance of DDR & High-Speed IO IP’s and perform failure analysis to root-cause a design problem. You with be working with IC design engineering, system engineering and Hardware applications engineering teams across the globe in a time critical environment.

Education Requirements

MTech, BTech or Equivalent in Electronics or Electrical Engineering with 1-3 years of related work experience

Skills/Experience

• Solid understanding of Electronics engineering fundamentals, DDR & High-Speed IO circuit analysis techniques and Semiconductor manufacturing process,
• Good understanding of Test and characterization methodology of DDR and High-Speed IO interfaces
• In-depth understanding of Mobile & PC DDR 2/3/4 protocol, timing diagrams, HSIO IPs PHY level understanding and Electrical parametric compliance specifications (eye diagram, differential signaling, jitter analysis, Receiver-Jitter-Tolerance, signal integrity, transmission line considerations, de-embedding).
• Hands-on experience using Bench instruments such as oscilloscopes, J-BERT, network / spectrum analyzers, signal generators and Logic analyzers is a must.
• Solid software skills for writing and debugging Test code using C, C# or Python. LabView knowledge is a plus.
• Using CAD software such as Mentor Graphics DA or Cadence Allegro is a plus.
• Ability to work effectively in a fast-paced environment with strong verbal and written communication skills.
  Keywords
  
  DDR, High-Speed IO, Electrical Spec compliance, Eye Diagram, Jitter, C, C#, Python, LabVIEW
  

Education

Minimum Qualifications

Bachelors - Computer Science, Bachelors - Engineering, Bachelors - Information Systems

Certifications

Work Experiences:

Skills

Preferred Qualifications

Education

Work Experiences:

1+ years experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. ,1+ years experience utilizing schematic capture and circuit simulation software. ,1+ years experience with circuit design (e.g., digital, analog, RF).

Skills

Computer Science, DSP Architectures, Electrical Engineering, Optical Systems, Packaging Systems

Applicants: If you need an accommodation, during the application/hiring process, you may request an accommodation by sending email to accommodationsupport

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