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仕事内容

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Engineer (Verification)

Work location: Bangalore

Job Description Summary

Design Verification expert with good subsystem and IP level verification. Must possess excellent debug skills. Expert in developing SV UVM based testbenches. Should have worked on time-bounded projects leading to Si realization.

Job Description

Design Verification expert with good subsystem and IP level verification. Must possess excellent debug skills. Expert in developing SV UVM based testbenches. Independently handle verification of subsystem/IP. Define methodology for subsystem/IP verification. Follow systematic approach of metric driven verification with meticulous attention to quality and completeness. Should be able work closely across teams to meet delivery timelines.

Required experience

  • Worked on Subsystem / IP level verification projects
  • Experience in ARM based designs is a plus
  • In-depth knowledge SV-UVM
  • Expertise in verification test plan development, test cases coding; Execute and debug test cases to achieve functional and code coverage goals
  • Experience in C based testcase development
  • Strong knowledge of AMBA protocols like AXI, ACE, APB, AHB.
  • Strong problem solving skills. Exhibit discipline, thoroughness and methodical approach in solving problems
  • Self-driven and committed individual who can work in a fast paced project environment
  • Prior experience with Cadence tools and flows is highly desirable
  • Familiarity with ARM/CPU v8 architectures and ARM SW Tool chain is a plus
  • Experience in developing c-based test cases for SOC verification
  • Good knowledge of some of the protocols like UART, I2C, SPI, JTAG
  • Embedded C code development and debug

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締切: 20-06-2024

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