Posição: Software Developer

Tipo de empregos: Full Time, Permanent

Experiência: 3 - 6 years

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Conteúdo do emprego

Roles and Responsibilities


  • Experience in implementing designs using VHDL/ Verilog/System Verilog.
  • An excellent knowledge of digital design techniques, strong analytical and debugging skills.
  • Knowledge of verification planning, verification flow, and methodologies.
  • Knowledge of any constrain random verification methodology.
  • Ability to write test cases, coverage and checkers at block and system level.
  • Ability to be good team player and adapt to situation.
  • Attention to details with clear verbal and written communication
    • Graphics knowledge.
    • Understanding of cache memory designs.
    • Knowledge of AXI bus protocols.
    • Knowledge of linting, Synthesis of IP and timing closure.
    • Experience with industry-standard EDA tools. (Cadence/Synopsys)
    • Understanding of scripting languages such as Python, Perl.
    • A Bachelors or Master’s degree in engineering with excellent academics.
    • At least 3+ years of experience


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    Data limite: 20-06-2024

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