Sr Engineer

Ver: 101

Dia de atualização: 06-05-2024

Localização: Noida Uttar Pradesh Hyderabad / Secunderabad Telangana Bengaluru / Bangalore Karnataka

Categoria: IT - Software

Indústria: Electronic Components Semiconductors

Posição: Team Lead/Technical Lead

Tipo de empregos: Full Time, Permanent

Experiência: 5 - 10 years

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Conteúdo do emprego

# 1 . SoC Design

Job Description:

4 to 20 years of work experience in ASIC/SoC Design
Experience in Logic design /micro-architecture / RTL coding is a must
Must have hands on experience with SoC design and integration for complex SoCs
Experience in Verilog/System-Verilog is a must.
Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC
Understanding of Memory controller designs and microprocessors is an added advantage
Work closely with the SoC verification and validation teams for pre/post Silicon debug
Hands on experience in Low power SoC design is required
Hands on experience in Multi Clock designs, Asynchronous interface is a must
Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required
Understanding of constraint development and timing closure is a plus
Experience in Synthesis / Understanding of timing concepts is a plus
Experience creating pad ring and working with the chip level floorplan team is an added advantage
Excellent oral and written communications skills
Proactive, creative, curious, motivated to learn and contribute with good collaboration skills#

# 2. Synthesis Sr. Engineer/ Lead

4-20 yrs experience in Synthesis and STA
Synthesis, Static Timing Analysis and LEC of SoC/Cores
Full chip and block level timing closure, IO budgeting for blocks
Logical equivalence check between RTL to Netlist and Netlist to Netlist
Knowledge of low-power techniques including clock gating, power gating and MV designs
Proficient in scripting languages (TCL and Perl)
ECO timing flow

# 3.STA Bangalore

# 4. Low Power - Sr. Engineer/ Staff Engineer

Job description

4 to 12 years of work experience in ASIC/SoC Design
Hands on experience in Low power SoC design is required
Hands on experience in Multi Clock designs, Asynchronous interface is a must
Experience in using the tools in ASIC development such as VCS, CLP and Primetime is required
Experience to independently drive all power related tasks like use case power generation, leakage and dynamic power estimations
Experience with structural low power checks like CLP and power aware functional verification
Experience in Synthesis / Understanding of timing concepts is a plus

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