Senior Verification Engineer

☞ Xilinx

Ver: 101

Dia de atualização: 06-05-2024

Localização: Hyderabad / Secunderabad Telangana

Categoria: Alta tecnologia IT - Software

Indústria: Semiconductors

Posição: Mid-Senior level

Tipo de empregos: Full-time

Salário: View Detail

Loading ...

Conteúdo do emprego

Xilinx is looking for a talented, self-driven and motivated software lead to be part of the Xilinx System Level Simulation Methodology and Tools team. The individual will focus on System Level Simulation and Verification flows and related automation within the tool framework. The framework is applicable to all Xilinx Design tools, namely Vivado and the various SDx Software Defined development environment. Vivado Tool Suite is Xilinx’s primary IDE that enables users to do System Level Design. It is a revolutionary design environment built to accelerate the design and verification of our ’All Programmable’ FPGAs, SoCs and 3D ICs. The SDx family of software defined development environment includes the SDAccel, the SDSoC and the SDNet tools.

As a member of this high-performance team, the selected candidate will be responsible for extending the Xilinx Vivado and Xilinx’s new SDx development environments to enable system level simulation and emulation infrastructure, debug and profile of the design. The candidate has opportunity to work on developing a new tool environment from an early stage and leave his/her personal mark on the tool. The selected candidate will take ownership of simulation related infrastructure and flows. He / She will ensure that these features meet technical specifications and business goals, and assume responsibility for improving the quality of the solution. The candidate will be involved in all aspects of product development; design, prototyping, testing, and productization.

The team provides a fast-paced start-up like environment offering each of its members immense opportunity to interact with a wide variety of people including from other organizations like marketing, sales, support, and even direct customer interaction, and truly learn and grow their skills and capabilities.

Qualifications:

  • B.Tech/M.Tech ECE/EEE
  • 6+ total of which 3+ years of experience in the verification of DDR memory protocols
  • Experience in specifying and developing the verification infrastructure for verifying processor based designs
  • Strong understanding of DDR memory protocols and system level use-cases
  • Strong analytical problem solving, and attention to details
  • Strong experience in HDL, verification, and general computational logic design/verification concepts
  • Knowledge of system-level architecture including buses like AXI/ACE/CHI, AMBA interconnects
  • Expertise in Verilog/System Verilog, UVM, Scripting languages like Perl/Python, etc.
  • Excellent written and verbal communication skills
  • Excellent interpersonal skills, self-motivated
Loading ...
Loading ...

Data limite: 20-06-2024

Clique para aplicar para o candidato livre

Aplicar

Reportar emprego
Loading ...
Loading ...

EMPREGOS SEMELHANTES

Loading ...
Loading ...