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Job content

Job Description


Roles and Responsibilities

5 years of work experience in ASIC RTL Design

Experience in Logic design/micro-architecture/RTL coding is a must.

Must have hands on experience with design and integration of complex multi clock domain blocks

Experience in AXI,Verilog/System-Verilog is a must.

Should have knowledge of AMBA protocols - AXI, AHB, APB, clocking/reset/debug architecture

Hands on experience in Multi Clock designs, Asynchronous interface is a must.

Understanding of DSP and microprocessors is an added advantage

Work closely with the Design verification and validation teams for pre/post Silicon debug

Hands on experience in Low power design is required

Experience in Synthesis / Understanding of timing concepts for ASIC is and added advantage.

Experience in using the tools in ASIC development such as Lint, CDC is required and Design compiler and Primetime is an added advantage.


Role:
Design Team Lead
Salary:
Not Disclosed by Recruiter
Industry:
Electronic Components / Semiconductors
Functional Area
Engineering - Hardware & Networks
Role Category
Hardware
Employment Type:
Full Time, Permanent
Key Skills

Apb

ASIC

Axi

Amba

Design Verification

Verilog

Lint

Ahb

RTL Coding

RTL Design

Education
UG:
Any Graduate

Company Profile

Mobiveil Technologies India Private Limited
A brief intro about Mobiveil

Mobiveil Inc is a fast growing technology company that delivers Silicon IPs and platform enabled solutions to semiconductor companies, OEMs, and design houses. Over the past 10 years, we had grown a solid team in Hardware/Embedded Software, Protocol Stack Development, ASIC Services & Testing Services. We also have a small team on Network protocol implementations.

From 5 to 10 year(s) of experience
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Deadline: 14-07-2024

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