Senior Digital Verification Engineer

☞ Cyient

View: 106

Update day: 06-05-2024

Location: Hyderabad / Secunderabad Telangana

Category: Telecommunications

Industry: Aerospace Defense

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Job content

Cyient is a global engineering and technology solutions company. As a Design, Build, and Maintain partner for leading organizations worldwide, we take solution ownership across the value chain to help clients focus on their core, innovate, and stay ahead of the curve. We leverage digital technologies, advanced analytics capabilities, and our domain knowledge and technical expertise, to solve complex business problems.

With over 15,000 employees globally, we partner with clients to operate as part of their extended team in ways that best suit their organization’s culture and requirements. Our industry focus includes aerospace and defence, healthcare, telecommunications, rail transportation, semiconductor, geospatial, industrial, and energy.

Job Description

Job Title

Senior Digital Verification Engineer

Job Summary

ASIC/FPGA verification planning, verification environment development and verification execution.

Key responsibilities

  • Owns the verification process in the project.
  • Features/Requirements extraction from the specification.
  • Verification planning.
  • Verification environment/testcase development.
  • Responsible for the quality of the verification.
  • Knowledge sharing among the digital design community and involvement in lessons learned and efficiency improvement forums.
  • Contributes to the achievement of the quality objectives as stated in the quality policy of AnSem.

Tasks

Verification

  • Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers.
  • Write a verification plan using random techniques and coverage analysis, and work with designers to ensure it is complete.
  • Develop tests and tune the environment to achieve coverage goals.
  • Own and debug failures in simulation to root cause problems.
  • Architecting, developing, and maintaining verification tools/methods to streamline the design of state-of-the-art SoCs/Chips.
  • Analysis/closure of code and functional coverage.
  • Work closely with architects/RTL designers to bring up a new architecture/micro-architecture on the verification environment.
  • self-contained tracking of efforts.

Reporting & Communication

  • reporting to team-lead and project management.
  • Knowledge sharing.
  • tracking of effort progress and immediate articulation of potential technical target achievement risks.

Other

  • skill-related duties as assigned and according to the priorities of the moment.

Quality

  • Is committed to complying with the requirements of the Quality Management System that are related to the job title and to possible changes of the system.
  • Is committed to developing and implementing AnSem/ Cyient Quality Management System and continually improving its effectiveness.
  • Uses AnSem/ Cyient issue tracking system to post customer complaints, non-conformities and quality improvement proposals.

Authorities

  • Self-contained Digital Verification engineering work within project constraints.

Job Requirements

Education/experience:

  • Master’s Degree in electrical engineering or equivalent experience.
  • Fundamental understanding of SoC design and CPU/DSP.
  • 4+ years of prior experience in verification is required.
  • Deep understanding of coverage, constrained-random, transaction level.
  • Experience with SystemVerilog, Assertions and UVM.
  • Experience with Gate level simulations.
  • Experience with C/C++.
  • Experience with python or a similar scripting language is a plus.

Mandatory competences

  • Technical: A basic knowledge of digital electronics.
  • Language: Fluency in English, both written and spoken.
  • Personal:
    • Excellent problem-solving and analytical skills.
    • Excellent planning & organizing skills.
    • Able to work in a team.
    • Stress-resistant and result-oriented.

Desirable

  • Experience with low power verification (CPF/UPF).
  • Experience with formal verification.
  • Experience with scan/testmodes verification.

Skills & Experience

Mixed Signal ASIC, RTL Design, SoC Design

Cyient is an Equal Opportunity Employer.

Cyient recruits, employs, trains, compensates, and promotes regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender, gender identity or expression, veteran status, and other protected status as required by applicable law. We are proud to be a diverse and inclusive company where our people can focus their whole self on solving problems that matter.

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Deadline: 20-06-2024

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