Position: Mid-Senior level

Job type: Full-time

Salary: View Detail

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Top3 Semiconductor Organization in the world

Senior SoC Firmware Developer

Location: Bangalore

Senior SoC Firmware Developer

Job Description

Our team is responsible for delivering state of the art FPGA system solution. As part of High-speed IO solution team, we develop extensive firmware stack for enablement of cutting-edge DDR/LPDDR subsystem. We are responsible for IO PHY calibration specifications, firmware code and memory validation tools. Most development happens pre-silicon and requires working closely with silicon design and validation teams for testing and support. During post silicon phase, engineer is expected to work with silicon validation team for productization. Senior Firmware developer needs to have good knowledge and working experience in memory related technologies and deep knowledge of the JEDEC specifications and IO PHY training steps, as well as pre and post silicon debugging experience.

Responsibilities:

� Review firmware spec and provide feedback to team.

� Develop firmware functions. Pass C language linting, Coverity check and code review with team.

� Perform unit and system level testing including failure analysis and debug of product issues as part of development and validation phases

� Develop test plan on both unit testing and pre-silicon verification

� Execute test plan. Debug in RTL simulation. Maintain regression.

� Support Emulation team for testing and debugging.

� Support silicon validation

Qualifications

� Experience or deep knowledge of DDR/LPDDR DRAM

� Ability to translate JEDEC specifications related to Memory and MIPI protocols into algorithms and drive hardware assisted training algorithm implementation

� RTL simulation and debugging, 3-12 years

� Firmware development and unit testing experience (C, GCC, Assembly), 3-12 years

� Tools and scripting (Python, shell) experience

Preferred Qualifications

� BS in Computer or Electrical Engineering or equivalent with 3-12 years of experience

� DDR/LPDDR DRAM and IO PHY training knowledge and experience

� Python, C++, Verilog

India, Bangalore

Contact: Uday Bhaskar

Mulya Technologies

"Mining the Knowledge Community"

Email id : muday_bhaskar@yahoo.com

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Deadline: 20-06-2024

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