Senior Verification Engineer

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Senior Verification Engineer

Pune, Maharashtra, India

Our client is a US Based startup founded by industry veterans with solid track record of technology innovation and business execution and deep domain expertise in multi-gigabit technologies. We are building advanced connectivity solutions for next generation autonomous driving systems featuring highly scalable, very high data-rate and secure end-to-end connectivity solutions to fuel the needs of AI processors and advanced sensors.

Job Description:

Job Description:

We are a diverse team of exceptional ASIC and systems engineers with several years of cumulative experience in Architecture, Logic design, Verification, Physical design, Hardware-Software co-simulation, FPGA Prototyping and Firmware development.

We are developing state-of-the art SoCs from architecture till final product involving automotive centric design methodologies and flows tailored for functional safety. We have presence across multiple geographies and are currently in search of a Principal level IP/SoC Design Verification Engineer.

Responsibilities:

• Architect and develop testbenches using System Verilog and UVM for functional and power aware RTL verification. Participate in defining verification strategy (Directed, Constrained random and Formal) for IP, sub-system and SoC verification.
• Develop UVM component like agents (active and passive), scoreboards and environment etc., Develop assertions, functional coverage.
• Develop test plan, UVM based test sequences, layered sequences, virtual sequencers.
• Drive closure of verification metrics to cover verification space. Work with team to identify and close gaps in functional, power aware and Gate level timing simulation.
• Develop C’ testcases for HW-FW simulation and FPGA prototyping.
• Regression setup, debug of RTL and gate level netlist.
• Review industry standard spec and augment test plan to improve quality of verification.
• Actively participate in post silicon bring up, validation and compliance testing and debug.
• Work collaboratively with cross-functional teams like ASIC Architect, ASIC Designers, firmware development team to ensure successful delivery of product.

Qualification:

• Proven track record of verification, taking several chips from specification to tape out.
• Proven expertise with UVM and/or System Verilog based verification.
• Excellent understanding of ASIC verification methodologies and proven experience of verification closure.
• Solid Understanding of standard ASIC verification techniques like
• Test Planning
• Testbench creation.
• Code and functional coverage
• Directed and constrained random stimulus generation and test.
• Low power verification. UPF/CPF Flow.
• Assertion based flows.
• UVM verification methodology or System Verilog testbench
• C/C++, Perl, Python scripting.
• Experience working with source control tools, bug management tools and release management tools such as Jenkins, Git, Jira.
• Experience with SoC interfaces, embedded processors, networking protocols, security protocols and video formats will be a big plus.
• Strong written and verbal communication skill and ability to work independently.
• Bachelors in Electrical Engineering or equivalent and 5+ years of experience
• Candidate is expected to have strong ability to take initiative, leverage problem solving skill to improve quality and completeness of verification and to able to work with diverse teams.

Contact: Uday Bhaskar

Mulya Technologies

"Mining the Knowledge Community"

Email id : muday_bhaskar@yahoo.com