Emulation Engineer

Job Description
Come join the Server Emulation Solutions team in Bangalore as a Emulation Engineer. In this role you will be working directly with the IP designers, Validation engineers, Firmware and SoC engineers to validate next generation Server IPs on a Reference SoC through emulation based modeling for future Intel SoCs. The Server Emulation Solutions team team enables future generations of IPs that power Cloud, Enterprise, and Data Center by delivering leadership IPs with high quality for our customers and Intel. Creates emulation/Field Programmable Gate Array - FPGA models from a Register Transfer Level - RTL design using emulation/FPGA synthesis, partitioning and routing tools. Defines and documents RTL changes required for emulation/FPGA. Develops hardware and software collaterals and integrates it with the emulation/FPGA model. Tests and debugs the emulation/FPGA model and collaterals. Defines and develops new capabilities and HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for functional validation as well as SW development/validation. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. Interfaces with and provides guidance to preSilicon Validation teams for optimizing preSi validation environments, test suites and methodologies for emulation efficiency. Develops and applies automation aids, flows and scripts in support of emulation ease of use and improvement of equipment utilization. Additionally, the person should be responsible for understanding architecture, play a critical role in developing testplan, come up with industry standard solutions to measure coverage, leading and developing a team of verification and validation engineers to create a motivated high-performance team.

Qualifications

Qualifications: Must have a Bachelor’s degree or Master’s degree in Electrical Engineering, Computer Engineering with relevant experience of at least 15+ years Job Experience: Technical experience in verification of RTL-based digital systems with very good understating of various system level flows Experience leading development of verification architecture based on evolving requirement from IP/SOC customers Experience with RTL design, Verilog and simulation, debug tools such as Verdi, System Verilog based verification techniques. Experience in debugging and isolation techniques including writing checkers, monitors, assertions and necessary DPI interfaces for co-emulation environments Experience in SW Programming/scripting and debug such as C, C++, Perl, Python Work experience creating a self-checking emulation/simulation test bench Highly proficient in UVM techniques for verification Hands-on experience of Emulation and simulation BFM based verification Good understanding of architectural design documents(micro-architecture documents, integration documents) Preferably good understanding of emulation/simulation platform with major vendors (Synopsys, cadence ) Protocol knowledge : PCIE, KTI, CXL, AMBA, DDR, RAS Good understanding of CPU architecture (Intel/AMD/Arm/GPU) Highly proficient with coherent, non-coherent and concurrent traffic validation Experience with emulation based systems such as Synopsys ZeBu, Cadence Palladium or Mentor Graphic Veloce or FPGA prototyping systems is a plus Experience in building emulation based models for large scale designs is a plus Job Responsibilities: Work closely with peers in architecture, design and verification teams Should be able to review the IP teams requirements, come up with verification plan, test plan, micro-arch, identify scenarios and design intent and develop verification strategies which can ensure defect free IP’s Maintain generic emulation based verification environment and regression setups for various IP’s Leads activities driving the development of various stimulus to support the emulation based verification of various IP’s Develop and maintain UVM environments for IP interfaces Work in cross-functional teams to deliver bug free features in a timely manner

Inside this Business Group

IP Engineering Group’s (IPG) vision Build IPs that power Intel’s leadership products and power our customer’s silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel’s silicon design process. IPG’s guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

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