水平: Design Engineer

工作类型: Full Time, Permanent

经验: 10 - 20 years

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工作内容

*Develop CPLD and FPGA for glue logic, including code, simulation, and verification.
*Capture the detailed design with schematic entry tools; generate the BOM and netlist.
*Work with Mechanical Engineer for thermal simulations, heat sink designs etc

Required Candidate profile

Mandat :

Experience working on more than 14 Multilayer

High speed design – 1G, 200G, PCIe 2,

Experience in working on Complex board designs from good product company
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最后期限: 20-06-2024

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