Design Verification Engr

☞ Texas Instruments

見る: 104

更新日: 06-05-2024

場所: Bengaluru / Bangalore Karnataka

カテゴリー: 電気/電子工学 生産/操作

業界: Manufacturing

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仕事内容

About TI
Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world’s brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We’re committed to building a better future – from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. Put your talent to work with us – change the world, love your job!
About the job

CTS (Clock and Timing Solutions) product line in India focuses on development of state of the art high performance
RF PLLs (20GHz and beyond), modulator/demodulator, BAW based oscillator, clock generator, Clock multipliers
(~40GHz) etc. The focus of the team is to create differentiated and high performance parts for Aerospace and
Defense market. These products are done in BiCMOS/CMOS processes. Whole product development happens in
India from Involvement in product definition to design, Verification, layout, silicon validation etc. We are looking for a
passionate, creative and self-driven engineer who could come up with innovative solutions to make a difference.


Job responsibilities:

The digital logic will contain one or more interfaces, Non-volatile Memories (NVMs) such as OTP, EEPROM or ROM,
state machines controlling overall operation as well sequencing of analog circuit such as various calibrations
(frequency, amplitude etc.)

As a Design engineer in the team, you will be working together with system/design engineers and understand the
digital architecture as well as full system (like understanding of usage of various system registers, sequence of
operations etc.) from DV perspective. You will be working independently on the development of constrained-random
verification environment using System Verilog and UVM for the digital systems. Will have to define and develop the
verification of complex digital design blocks by fully understanding the design specification and interacting with
design engineers to identify important modes and verification scenarios
  • Develop the DV environment, behavioural models of interfaces, development of RAL models for UVM
verification, put in place UVM components (like monitors, drivers, scoreboards etc.)
  • Identify the testcases needed, develop the test plan, write the testcase
  • Simulate the full chip design using analog models and RTL.
  • Debug tests with design engineers to deliver functionally correct design blocks.
  • Identify and write all types of coverage measures for stimulus and corner-cases.
  • Close coverage measures to identify verification holes and to show progress towards tape-out
  • Run the Gate Level Simulations (GLS)

Minimum requirements
  • Bachelors or Masters degree in Electronics/Electrical engineering.
  • 1-2 years Verification experience using UVM environment
  • Experience with: System Verilog, UVM
  • Working experience with Cadence DV tools
  • Experience in building testbenches, checkers and other ways to automate verification

Preferred qualifications:
  • Hand on experience in Gate level simulations
  • Scripting (Shell, Perl,…) is desirable
  • Verification experience on I2C, SPI
  • Experience in mixed signal simulation
  • Effective communication skills to interact with all stakeholders.
  • Ability to communicate effectively, and accommodate requirements of team members in other disciplines,
including analog hardware, validation & system engineering.
  • Been part of full device PG cycles, and exposure to verification of FW based digital systems
  • Design experience in memory interface controllers for RAM, ROM, OTP and Flash
To be considered for this position, please apply.
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締切: 20-06-2024

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