Physical Design Lead

☞ Intel

View: 107

Update day: 06-05-2024

Location: Bengaluru / Bangalore Karnataka

Category: Electrical / Electronics Legal / Contracts Production / Operation

Industry:

Loading ...

Job content

Job Description
Charter of the CLE-India CFE team in Programmable solutions group is to do SoC’s for its line of products.

Seeking an individual who has technical expertise in the RTL to GDSII Implementation of the ASIC design flow
The position calls for execution/implementation of projects either at Sub-system level and/or SoC level
The role requires interaction with various SoC team like FE/RTL/DFT/PD/STA team, Flow/Methodology team and other teams working on the SoC/Product
Working with tool/flow owners and vendors for ongoing tool/methodology improvement with an objective to meet the SoC/Product specs

The responsibilities will focus on the RTL to GDS flow and may include but not be limited to

SDC/Constraint understanding, generation, clock and timing closure
Synthesis with Synopsys Design Compiler DCT or industry equivalent
Low Power Domain Analysis using standard Power Formats UPF/CPF
Place and Route and clock tree synthesis with Synopsys ICC2 or equivalent tools
Static Timing Analysis with Synopsys Primetime or equivalent tools
Formal equivalence checks
Layout Verification and DRC analysis
Static/Dynamic IR analysis, power network analysis, reliability analysis

The ideal candidate should exhibit the following behavioral traits
Strong verbal and written communication skills
Work co-ordination and collaboration working with global teams
Strong initiative and analysis/problem solving skills
Able to work in a diverse team environment
Motivation and drive to continuously push design convergence and productivity
Ability to work independently and lead a team
Work planning and schedule tracking


Qualifications

A Bachelor or Masters of Engineering degree in Electrical/ Electronic/VLSI Engineering or related field
8 or more years of ASIC/SoC/Chip design industry experience of implementation at IP/Sub-system and SoC’s level
Experience in driving activities from Logic Synthesis, STA, Physical design, layout verification
Good understanding of timing convergence process and proven track record in resolving physical design issue like placement, congestion, CTS, routing
Should be able to corelate timing closure issues with place and route tools
Conversant with low power designs implementation, IR/EM analysis.
Hands on with EDA industry standard place and route tools from Synopsys and Cadence
Should have led design activities in the past
Perl/TCL or any scripting language knowledge

Inside this Business Group


The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera’s industry-leading FPGA technology and customer support with Intel’s world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.


Legal Disclaimer:

Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.comand not fall prey to unscrupulous elements.

Loading ...
Loading ...

Deadline: 20-06-2024

Click to apply for free candidate

Apply

Report job
Loading ...
Loading ...

SIMILAR JOBS

Loading ...
Loading ...