Senior Circuit Design Engineer

☞ Intel

View: 101

Update day: 23-04-2024

Location: Bengaluru / Bangalore Karnataka

Category: Electrical / Electronics

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Job content

Job Description
The position is part of Platform Enablement Solutions Group (PESG) - Technology Enablement Group (TEG) The charter of the group is to enable external foundry ecosystem to the product design teams across various domains - focused on providing optimum IP solutions - including standard cells, memories, IO, ESD EDM and other design collaterals. We work in a highly collaborative environment, interfacing with design teams throughout Intel in a fast paced environment where thinking out of the box is encouraged and rewarded Job Description - This position is for senior standard cell circuit design engineer. Selected candidate will drive Concepts of transistor level circuit design implementation PPA analysis and validation Collaborating with all relevant teams Playing a strategic role of building PPA optimized ,functional and cost-effective Intel world-class products. Candidate will have the opportunity to integrate and come-up with new ideas, as well as work with a team of smart engineers. As a Standard Cell Design Engineer for the custom circuits team, candidate will perform the following Engage with Intel Design teams on standard cells requirements Engage with external foundry to understand and get standard cells development requirements Develop standard cell circuits that push Intel design PPA Drive library architecture, circuit design discussions and optimization effort to improve overall Library PPA Drive layout optimization effort by identifying and optimizing transistors sizes and parasitic to push circuit PPA Work on Library PPA for different technology, architecture, PDK releases. Work and guide other circuit design engineers and layout design engineers to develop best optimized and cost effective std cell library


Qualifications

BE/B.Tech/ME/M.Tech/MS in Electrical or Electronics Engineering Experience: 3-7 years We are looking for applicants with experience in Standard Cell circuit design of high-performance flip flops, latches, multibit flip flops, voltage level shifters, power management cells ,Clock cells ,retention flip flops and other complex circuits. Strong understanding of CMOS device characteristics and design rules. Knowledge of deep submicron process issues and Finfet Technologies Strong understanding of Digital circuits and optimization for better PPA. Good layout design knowledge and parasitic optimization in various types of layouts. Hands-on experience running SPICE simulations and high sigma variation analysis. Hands-on experience running circuit reliability checks [EM,Aging] Hands-on experience in developing and validating std cell circuits KPI’s for functional robustness and PPA optimization Understanding of Timing characterization and modeling of Standard cell circuits. Strong proficiency in scripting languages like Perl, Python, and Tcl. Great teammate with solid communication and analytical skills. Understanding of ASIC flow is plus

Inside this Business Group


Product Enablement Solutions Group (PESG) is one of the key pillars, enabling Intel product design teams get to market faster with winning leadership products.


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Deadline: 07-06-2024

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