Physical Design Engineer

☞ Capgemini

看过: 101

更新日: 28-05-2024

位置: Hyderabad / Secunderabad Telangana

类别: 电气/电子 电信

行业: Information Technology

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工作内容

Physical design : 3 – 10 years

Location: Bangalore, Hyderabad, Noida, and Coimbatore.

Desired Skills:

  • Chip level floorplanning, partitioning, timing budget generations, power planning, top PnR, CTS, block integration and ECO generation.
  • Hands on experience in ICC and primetime.
  • Block level implementation from netlist to GDS.
  • Handling timing closure of high frequency blocks.
  • Expertise in signoff closure – Timing with SI and OCV, Power, IR and physical verification at both block and chip level.
  • Handling blocks of high instance counts – 1M instance and above.
  • Understanding constraints and fixing techniques.
  • Understanding SI prevention, fixing methodology and implementation.
  • Proficient in layout edit techniques.
  • Proficient in Synopsys ICC or Mentor Olympus and Atoptech tool set.
  • Experience in Design Automation and UNIX system.
  • Experience in Tcl/ PERL is a plus.

2)Senior Manager – Physical Design

Experience: 10 to 20 years

Description:

Manage and lead a team of physical design engineers. Job also entails significant amount of hands-on work, in particular place-and-route, static timing analysis, formal verification, physical verification, and power analysis. Drive implementation of physical design methodologies as required through the development of automation scripts. Work with front-end engineers to resolve timing and power issues. Evaluate new tools, and creatively drive power reduction of designs. Must be proficient and highly capable in floorplanning and time budgeting.


Desired Skills & Experience:

  • Experience level 10 to 15 years.

  • Must possess 10+ years of hands on experience in handling block/chip level implementation from Netlist to GDS

  • Must possess hands on experience in timing closure and physical verification closure

  • Must have handled blocks of sizes 1M instances and above at frequencies higher than 1GHz

  • Experience in handling lower tech nodes that include 40nm, 28nm or lesser nodes etc.

  • Must have hands on tapeout experience in lower tech nodes in any of the tools mentioned such ICC or SOC Encounter.

  • Must have the ability to think on the spot for quick solutions and work-around at the time of tapeout to hit the schedule on time

  • Must possess excellent scripting skills – TCL or Perl

  • Experience in Synthesis and Formal is a plus

  • Excellent verbal and written communication skills are required.

  • Must possess excellent debug skills, analytical skills and the ability to work independently.

  • Must be highly motivated and possess excellent team spirit


Education: UG – B.Tech/B.E. Electronics/Telecommunication, Electrical) OR (PG – M.Tech/M.E, Electrical, Electronics/Telecommunication)

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最后期限: 12-07-2024

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